TUSB1210 data sheet, product information and support | TI.com
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
HSIC USB 2.0 PHY IP
The Next-Generation Interconnect | Mouser
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB 3.0 PHY IP Core
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
PCIe/USB/SATA PHY Appilcation example | Renesas
Canovatech - CT25201_PHY
The USB 2.0 Device IP core | Arasan Chip Systems
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
USB 2.0 PHY IP core | Arasan Chip Systems
Hi-Speed USB interfacing
USB 2.0 Device Controller for SoC Designs | Cadence IP
Confidently Characterize Validate and Debug Your USB 31 Electrical PHY Designs | Tektronix
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 Solutions | Arasan Chip Systems
USB 2.0 PHY Verification
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 PHY for SoC Designs | Cadence IP
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
